In modern high-speed digital systems, many digital IC chips are mounted on a printed circuit board. These may include a signal transmitter IC chip and a signal receiver IC chip which are connected via wired lines (printed circuit lines). With increased circuit density and signal speed, the performance of the driver included in the transmitter IC chip is crucial to meet the requirements of timing margin, signal integrity, noise immunity, low electromagnetic interference (EMI) emissions, low cross-talk, and low power dissipation. Preferably, the driver is single-ended rather than differential thereby reducing the pin count and power dissipation.
Existing digital driver designs meet some but not all of the above mentioned criteria. Typical CMOS and TTL drivers have large voltage swings. Consequently they tend to be noisy and exhibit very high power dissipation with moderate capacitive loads. Also, even with slew rate control, EMI emissions are relatively high and timing margins are inadequate for many applications. Although many of the criteria are met by typical ECL/CML (Emitter Coupled Logic/Current Mode Logic) drivers, power dissipation is very high.
U.S. Pat. No. 5,023,488 granted on Jun. 11, 1992 to William F. Gunning discloses a bidirectional transceiver having a driver and a receiver. The transceiver interfaces VLSI CMOS circuits to transmission lines via which a digital voltage signal is transmitted. Due to a high rise and fall time of the 0 transmitted signal, large voltage spikes are present resulting in high EMI emissions and high power dissipation.
Another known technique is current loops (current out/current in). They have traditionally been used in noisy environments such as used with Teletype which is a low speed application. Another technique used in very high speed applications is the electro-optical interface of a laser diode transmitter and a photo diode receiver. This interface is expensive and consumes additional chip area.